Integration of Twin Models in UVM Verification IPs for Space Telecommunication Systems

Abstract

In the dynamic fields of semiconductor design and digital system development, effective verification procedures are in high demand. In particular, functional verification is essential for space systems to guarantee mission success, prevent errors in intricate environments, and uphold the reliability vital for effective space exploration. Testing phase results extremely challenging because of the high complexity of systems, often due to the intricate interplay of hardware, software, and environmental factors, impeding comprehensive validation. This paper presents an innovative methodology for the functional verification of systems involved in space telecommunications: this is based on the development and integration of software Twin Models within advanced and automated verification environments, with the dual purpose of simplifying the stimulation of the Design Under Test (DUT) and producing instant-by-instant expected behavior. The proposed solutions are developed in SystemVerilog Hardware Verification Language (HVL) and are fully compliant with Universal Verification Methodology (UVM) standard. As proof of the effectiveness and applicability of this approach, examples of verification environments for different systems are given, including high-speed interfaces, such as SpaceWire (SpW) CODECs, and high-speed encoders and modulators for both Direct-to-Earth and inter-satellite communications applications. A test campaign was conducted for all these systems, and using the Twin Models made it possible to achieve 100% of both functional and code coverage. The final result is a significant simplification in the creation of tests and DUT debugging and a very highly flexible, self-checking, and automated verification environment able to test any possible DUT configuration efficiently.

Keywords

• Twin model
• verification
• SystemVerilog
• UVM
• space
• telecommunications