Open Computer Science (Dec 2013)

PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC

  • Rahimunnisa K.,
  • Karthigaikumar P.,
  • Christy N.,
  • Kumar S.,
  • Jayakumar J.

DOI
https://doi.org/10.2478/s13537-013-0112-2
Journal volume & issue
Vol. 3, no. 4
pp. 173 – 186

Abstract

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Keywords