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Open Computer Science
(Dec 2013)
PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC
Rahimunnisa K.,
Karthigaikumar P.,
Christy N.,
Kumar S.,
Jayakumar J.
Affiliations
Rahimunnisa K.
Department of Electronics and Communication Engineering, Karunya University, Coimbatore, 641 114, India
Karthigaikumar P.
Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, 641 032, India
Christy N.
Department of Electronics and Communication Engineering, Karunya University, Coimbatore, 641 114, India
Kumar S.
Department of Electrical and Electronics Engineering, Dr. NGP Inst. of Technology, Coimbatore, 641 048, India
Jayakumar J.
Department of Electrical and Electronics Engineering, Karunya University, Coimbatore, 641 114, India
DOI
https://doi.org/10.2478/s13537-013-0112-2
Journal volume & issue
Vol. 3, no. 4
pp. 173 – 186
Abstract
Read online
No abstracts available.
Keywords
cryptography
aes
fpga
asic
parallel sub-pipelined
throughput
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