An Optimized Cyclic Weight Algorithm of (47, 24, 11) QR Code and Hardware Implementation

Abstract

This paper proposes an optimized cyclic weight (OCW) decoding algorithm based on novelty ideas. The OCW algorithm utilizes the properties of quadratic residue (QR) codes and the advantages of the syndrome-weight algorithm to facilitate fast decoding of the binary systematic (47, 24, 11) QR code. The memory size of the OCW algorithm is reduced to only 0.45% of that in the original cyclic weight algorithm. In addition, it can be carried out in simple and repeatable steps, which is of great importance for hardware implementation. We further propose a hardware architecture in ALTERA STRATIX V FPGA by adopting parallel processing and pipeline techniques. To the best of our knowledge, it is the first hardware architecture to decode (47, 24, 11) QR code. The synthesized results in ALTERA QUARTUS V17.0 show that the proposed hardware architecture operates at high throughput and low latency. The proposed hardware module may be a good candidate in 5G wireless communications.

Keywords

• Decoding
• pipelines
• architecture
• quadratic residue code
• cyclic weight algorithm
• FPGA