Low‐leakage track‐and‐hold buffer in 130‐nm CMOS with open‐gate FET bias

Abstract

Abstract The goal of this research is to design, fabricate, and test an amplifier circuit which minimizes the input bias current over the input direct current operating point of the amplifier. A biasing scheme to set the drain‐source voltage (Vds) to null the net gate leakage current of the input transistor is shown. The desired Vds bias is obtained by replicating the Vds of a reference transistor that operates at the same current density as the input transistor and has its gate terminal open‐circuited so that the drain‐gate leakage and the gate‐source leakage must cancel. An implementation of this scheme as a cascode amplifier is described. Measurement results are presented showing > 20× reduced drift rate of a track‐and‐hold circuit when the output buffer amplifier uses the new approach as compared with a conventional buffer amplifier.