A High Current Efficiency Two-Stage Amplifier With Inner Feedforward Path Compensation Technique

Abstract

A high current efficiency two-stage amplifier with inner feedforward path compensation (IFPC) technique is proposed in this paper. To improve the current utilization of the whole structure, the recycling folded cascode amplifier (RFC) is adopted as the first stage, and the inner feedforward path which is used to eliminate the non-dominant pole is composed of the input stage of RFC and the tail current transistor of the second stage amplifier. By using the IFPC technique, the proposed amplifier achieves an extended gain-bandwidth (GBW) and sufficient phase margin (PM) compared to that of the two-stage amplifier using single Miller compensation (SMC). Moreover, this compensation technique avoids extra power consumption since it does not require additional circuits. The proposed two-stage IFPC amplifier was fabricated in a 0.18 μm CMOS technology and the chip area of it is about 0.076mm2. The simulated open loop AC response shows the DC gain, GBW, and PM are 130dB, 2.01MHz, and 58.3°, respectively. Measured results of transient response show when driving a 120pF load capacitance, the proposed amplifier achieves 368ns average 1% settling time, and about 1.56V/μs average slew rate (SR). Note that under the condition of 1.8V power supply, the power consumption is only 108μW, proving the proposed two-stage IFPC amplifier can achieve high current efficiency while maintaining stability.

Keywords

• Two-stage amplifier
• current efficiency
• frequency compensation
• inner feedforward path