A 3-Phase Reduced Switch Count Symmetric 17-Level Inverter Topology Supplying a Resistive Load

Abstract

Abstract The work explored in this paper includes the simulation analysis pertaining to a 3-phase symmetric cascaded H-bridge configured multilevel inverter, capable of producing 17-levels of output voltages with lower number of switching devices, supplying a resistive load. The proposed inverter topology is implemented using Carrier Overlapping Pulse Width Modulation (COPWM), Variable Frequency PWM (VFPWM), and Phase Disposition PWM (PDPWM) techniques with sine wave reference. The losses due to switching and harmonic components in the output voltage are found to be low in the proposed multilevel inverter. The Matlab/Simulink platform is used to validate the performance of the inverter. The switching loss calculation, and the percentage value of THD (Total Harmonic Distortion) occurring in the inverter output voltage and currents are shown for the above mentioned PWM methods using modulation index parameters. The simulation results illustrate that the proposed inverter implemented with PDPWM methodology produces lower amount of harmonics in the inverter output voltage and current, and the inverter implemented with COPWM technique produces output voltages of higher RMS values of fundamental frequency.

Keywords

• 17-level inverter
• COPWM
• Matlab/Simulink
• PDPWM
• Reduced switching devices
• Switching loss
• Total Harmonic Distortion
• VFPWM