A new radiation-hardened architecture for holographic memory address calculation

Abstract

Architectures for the memory address calculation unit of a holographic memory device have been deeply analyzed in the literature. Finite-precision analysis and the selection of parameters to ensure a discrepancy between the hologram plane and the observation plane of less than 1% has been performed by other designers. However, a fault-tolerant architecture implemented on field-programmable gate array (FPGA) for an Optically Reconfigurable Gate Array has not been proposed yet. Due to the importance of this unit in environments with high levels of radiation, such as robots in nuclear disasters or satellites in space, which are the most common applications, there is a real interest in protecting this hardware. This work introduces two main contributions: i) replaces the calculation of distances through a Coordinate Rotation Digital Computer (CORDIC) unit in order to save area and ii) improves the ratio of fault-detection and extends the input range of the trigonometric computations to exploit more efficient error detection techniques. The derived architecture allows us to recover the FPGA from a faulty behavior in 95% of the cases, which avoids waiting for slower processes such as scrubbing. This real-time detection only requires an extra area of 13% with respect to the unprotected circuit and does not include any loss of precision compared to previous designs.

Keywords

• Error detection
• holographic data storage
• FPGA
• Memory protection