FPGA-Based Implementation of Ship Detection for Satellite On-Board Processing

Abstract

At present, the raw echo data captured by spaceborne synthetic aperture radar is usually downlinked to the ground stations for imaging and analysis. If the SAR data can be processed on-board, the processing results could be transmitted to users directly through broadcast distribution, which can greatly reduce the delay time for emergency applications. However, on-board processing implementation faces many challenges due to the space radiation environment and limited resources of the satellite. In this article, a field programmable gate array (FPGA)-based implementation of ship detection for on-board processing is proposed, which has high efficiency in logic and memory resources. First, the hardware-oriented clustering approach is proposed. Image processing operations with similar regularity of data access can be mapped in one processing engine, which can reduce the employment of logic resources. Second, the concept of the data-buffering cycle (DBC) is proposed. The DBC provides a method to analyze the intermediate data and optimize the memory reuse. Finally, based on the above optimization methods, the FPGA-based implementation for a ship detection algorithm is presented. Compared with the traditional methods, the experimental results show the efficacy of our proposed method with lower consumption in logic and memory resources.

Keywords

• Field programmable gate array (FPGA)
• on-board processing
• processing engine
• ship detection