Radix-2^{<italic>k</italic>} MSC FFT Architectures

Abstract

In recent years, the SC FFT architecture has become popular for processing serial data. It requires a small number of components and achieves full utilization of the butterflies, which improves previous serial FFT architectures. By contrast, the MSC FFT architecture, which is the parallel version of the SC FFT, has not been studied in depth in the literature and it has not been analyzed if this new type of FFT architecture improves previous parallel FFTs. The aim of this paper is to provide a rigorous study of MSC architectures that expands the field of FFT architectures by incorporating fundamental knowledge about this promising FFT. With this goal, this paper proposes new MSC FFT architectures for any FFT size, radix, and parallelization. In order to derive these architectures, efficient modules have been developed. These modules are connected by permutation circuits to create the architectures. The optimization of the modules results in a reduction in the number of rotators and their complexity compared to previous designs. As a result, the proposed architectures not only achieve high throughput due to their parallel nature but also the lowest hardware complexity among parallel pipelined FFT architectures so far. To verify the architectures and compare the proposed approach to previous works, a 1024-point MSC FFT architecture has been implemented. Experimental results show that the architecture achieves a throughput of 1.32 gigasamples per second, and reduces the area and power consumption significantly with respect to previous designs.

Keywords

• Fast Fourier transform (FFT)
• multi-path serial-commutator (MSC)
• pipelined architecture
• radix-2k