A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis

Abstract

High-level synthesis (HLS) is a solution for rapid prototyping of application-specific hardware using the C/C++ behavioral programming language. Designers can apply HLS directives to optimize hardware implementations by making trade-offs between cost and performance. However, current HLS tools do not provide reliable quality of results (QoR) estimates, which prevents designers from making these trade-offs efficiently to ensure that the design meets the constraints. Taking advantage of the widespread use of machine learning (ML) to improve the predictability of electronic design automation (EDA) tools, we propose several graph neural network (GNN)-based models that learn and predict the post-implementation QoR from the pre-schedule control data flow graph (CDFG) representation of an HLS design targeting field-programmable gate array (FPGA) implementation, considering also the user HLS optimization directives. Experimental results show that our model can estimate the timing and resource usage of a previously unseen design (i.e, a completely new CDFG) within milliseconds with high accuracy, reducing prediction errors by up to $\mathrm {74~\%}$ compared to the estimate generated by the Vitis HLS tool itself after going through time-consuming scheduling and binding, and by $\mathrm {29~\%}$ and $\mathrm {22~\%}$ for resource usage and timing prediction, respectively, compared to the state-of-the-art.

Keywords

• Electronic design automation (EDA)
• graph neural network (GNN)
• machine learning (ML)
• high-level synthesis (HLS)
• quality of results (QoR)
• field-programmable gate array (FPGA)