Optimization of process parameter variations on leakage current in in silicon-oninsulator vertical double gate mosfet device

Abstract

This paper presents a study of optimizing input process parameters on leakage current (IOFF) in silicon-on-insulator (SOI) Vertical Double-Gate,Metal Oxide Field-Effect-Transistor (MOSFET) by using L36 Taguchi method. The performance of SOI Vertical DG-MOSFET device is evaluated in terms of its lowest leakage current (IOFF) value. An orthogonal array, main effects, signal-to-noise ratio (SNR) and analysis of variance (ANOVA) are utilized in order to analyze the effect of input process parameter variation on leakage current (IOFF). Based on the results, the minimum leakage current ((IOFF) of SOI Vertical DG-MOSFET is observed to be 0.009 nA/µm or 9 ρA/µm while keeping the drive current (ION) value at 434 µA/µm. Both the drive current (ION) and leakage current (IOFF) values yield a higher ION/IOFF ratio (48.22 x 106) for low power consumption application. Meanwhile, polysilicon doping tilt angle and polysilicon doping energy are recognized as the most dominant factors with each of the contributing factor effects percentage of 59% and 25%.

Keywords

• Analysis of variance
• DG-MOSFET
• SNR
• SOI