Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Abstract

The development of memristor‐based stateful logic circuits can minimize data movement during the computing process to achieve in‐memory computing, mitigating the von Neumann bottleneck in the current computing architecture. Herein, a method to combine resistance–resistance (R–R) and voltage–resistance (V–R) logic gates to implement exclusive logic gates composed of APMR‐two‐2(XOR, IMP, RIMP) and APMR‐three‐4XOR, where APMR means antiparallel memristors with a series resistor, is suggested. The proposed gates can accelerate XOR logic operation in a single cycle and expand for the n‐bit input. The performance of the proposed logic gate is then demonstrated with a 1‐bit full adder–subtractor along with the comparison of an n‐bit ripple carry adder. It shows that the implementation for the n‐bit adder takes 4n+1 memristors within 2n+1 steps, which significantly improves the optimization in terms of space‐ and time‐related costs compared with other memristive logic gates. Subsequently, the improved adder circuit can be further utilized to implement an n‐bit multiplier. In addition, the evaluation of the device stress on the various logic gates confirms that the proposed logic gates are reliable.

Keywords

• arithmetic operations
• in-memory computing
• logic cascading
• memristors
• nonvolatile memory
• sequential logic