Analysis of the Influence of Silicon-on-Insulator Lateral Double-Diffused MOS Device Substrate Deep Depletion on the Transient Breakdown Voltage

Abstract

With two-dimensional device simulation software, the influence of the deep depletion (DD) of the silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) device substrate on the transient breakdown voltage (TrBV) was analyzed. Based on the changes in the characteristics of the charge distribution and the depletion layer in the device substrate with time and the related parameters in the off state, the mechanism of their action on the transverse and vertical breakdown voltages (BVs) was studied. TrBV demonstrates completely different characteristics from the static breakdown voltage (StBV) due to the DD effect of SOI LDMOSs. Low drift region concentration (Nd) and substrate doping concentration (Psub) are conducive to obtaining a high maximum TrBV. With increasing drain voltage (Vd), the turn-off nonbreakdown time (Tnonbv) of the device with higher Psub decreases faster. However, the Tnonbv with higher Psub is higher at low Vd. Therefore, the maximum Tnonbv can be obtained by optimizing Nd and Psub under a given Vd. In addition, Tnonbv is greatly reduced with increasing temperature.

Keywords

• Silicon-on-insulator (SOI)
• MOS devices
• deep depletion (DD)
• breakdown voltage (BV)