Research of the Efficiency of High-Level Synthesis Tool for FPGA Based Hardware Implementation of Some Basic Algorithms for the Big Data Analysis and Management Tasks

Abstract

The article is devoted to a research of an effectiveness of high-level synthesis approach, based on Xilinx's high-level synthesis tool - Vivado, for a hardware implementation of sorting algorithms, which are one of the key algorithm for Big Data analysis, Data Mining, Data Storage and Management. Performance and hardware costs are the measures of the effectiveness in the provided research. The research methods are simulation and comparative analysis. Effectiveness of software implementation of the selected sorting algorithms based on a universal processor is compared with effectiveness of hardware implementation of the same sorting algorithms, obtained by high-level synthesis procedure with help of Xilinxs synthesis tool. The article discusses approaches to optimize the description of the sorting algorithms and assignments in boundaries of high-level synthesis procedure to achieve optimal effectiveness of the final hardware solutions. The article shows that the main effectiveness gain is provided by: the internal features of the sorting algorithm, selected for hardware implementation; the ability to parallelize the processing of the source arrays, which is achieved both by the settings of the Vivado synthesis tool and description style used for source code. Article summarizes research results and provide a direction for the future research works.

Keywords

• sorting algorithms
• high-level synthesis
• reconfigurable hardware accelerator
• hardware acceleration
• fpga
• big data analysis
• data management
• heterogeneous high performance computing