Investigating the Device Performance Variation of a Buried Locally Gated Al/Al₂O₃ Graphene Field-Effect Transistor Process

Abstract

In this study, a process is developed for the fabrication of buried top-gated graphene transistors with Al2O3 as a gate dielectric, yielding devices that can be suitable for not only flexible electronics but also laser-induced graphene (LIG)-based technology implementations. A new processing option is presented with the use of tetraethyl-orthosilicate (TEOS) as an etch stop for contact via etching of Al2O3. Buried locally gated Al/Al2O3 graphene field-effect transistors (GFETs) are fabricated with Dirac points as low as 4 V, with a metal-to-graphene contact resistance as low as ∼1.7 kΩ·µm, and an average hole mobility of 457.97 cm2/V·s with a non-uniformity of 93%. Large device variation and non-uniformity in electrical performance are not uncommon for graphene-based devices, as process-induced defects play a major role in such variation. AFM, SEM, Raman spectroscopy, and model fitting indicated that the rough Al/Al2O3 surface was the main factor for the observed device variation. AFM analysis indicated a graphene surface roughness Ra of 16.19 nm on top of the buried Al/Al2O3 gate in contrast to a Ra of 4.06 nm over Al2O3/SiO2. The results presented indicate the need to reduce device variability and non-uniformity by improving transfer methods, as well as the use of smoother surfaces and compatible materials. The presented analyses provide a framework with which other researchers can analyze and correlate device variation and non-uniformities while methods to reduce variability are investigated.

Keywords

• graphene
• graphene field-effect transistors
• 2D materials
• gate dielectric
• mobility
• Dirac point