Transitioning to UVM from VMM

Abstract

This paper discusses the process of transitioning to a UVM design verification environment for current VMM users. Differences and parallels between the two verification methodologies are presented to show that updating to UVM is mostly a matter of learning a new DV syntax. Topics include UVM phases, agents, TLM ports, configuration, sequences, and register models. Best practices and reference resources are highlighted to make the transition from VMM to UVM as painless as possible.