Large-capacity and high-speed instruction cache based on divide-by-2 memory banks

Abstract

An increase in the cache capacity is usually accompanied by a decrease in access speed. To balance the capacity and performance of caches, this paper proposes an instruction cache (ICache) architecture based on divide-by-2 memory banks (D2MB-ICache). The control circuit and memory banks of D2MB-ICache work at the central processing unit (CPU) frequency and the divide-by-2 CPU frequency, respectively, so that the capacity of D2MB-ICache can be expanded without lowering its frequency. For sequential access, D2MB-ICache can output the required instruction from memory banks per CPU cycle by dividing the memory banks with a partition mechanism and employing an inversed clock technique. For non-sequential access, D2MB-ICache will fetch certain jump instructions one or two more times, so that it can catch the jump of the request address in time and send the correct instruction to the pipeline. Experimental results show that, compared with conventional ICache, D2MB-ICaches with the same and double capacities show a maximum frequency increase by an average of 14.6% and 6.8%, and a performance improvement by an average of 10.3% and 3.8%, respectively. Moreover, the energy efficiency of 64-kB D2MB-ICache is improved by 24.3%.

Keywords

• Cache capacity expansion
• Divide-by-2 frequency
• Instruction cache (ICache)
• Inversed clock