Design and analysis of optimized dynamic comparator circuit for low-power and high-speed applications

Abstract

A typical dynamic comparator consists of two stages: A first stage comprising a differential amplifier and a second stage comprising latch-based circuitry. The primary function of the differential amplifier is to amplify the input difference, while the latch is responsible for the comparison process. Depending on the comparison result, the latch generates logic 0 or logic 1 at its output. In this research article, we have proposed a technique that will help to reduce the dynamic power consumption of the pre-amplifier stage output. The designer has two modes of operation and designs. Firstly, if the priority is to save dynamic power, use a modified dynamic comparator. Secondly, if his priority is to reduce delay, use an optimized modified dynamic comparator. According to designer specifications, this technique can be beneficial for low-power and high-speed real-time applications, especially battery-operated devices. Simulations were conducted using the Cadence Virtuoso tool to evaluate the effectiveness of the proposed method. The simulations considered a CMOS technology node of 90 nm with a length of 180nm. Various comparator circuits were analyzed in terms of their power consumption and delay. All the circuits were designed to operate with a clock frequency of 500 MHz, enabling effective control of the two stages of the comparator. Additionally, these circuits were designed to accommodate rail-to-rail input common-mode voltage.

Keywords

• Dynamic comparator
• Preamplifier
• High-speed
• Latch
• Low-power
• Analog-to-digital converter (ADC)