Planar Dual‐Gate Paper/Oxide Field Effect Transistors as Universal Logic Gates

Abstract

Abstract Electronics on paper enable some specific applications out of conventional ones which require innovative approaches and concepts on the design of devices and systems. Within this context, this work demonstrates that a unique set of characteristics can be combined in planar dual‐gate oxide–based field effect transistors with a back floating electrode using paper simultaneously as substrate and dielectric. The working principle of these transistors relies on the formation of electric double layers at the semiconductor/paper and paper/back floating electrode interfaces (associated to ions displacement within the paper) that can be disturbed by a voltage applied at a secondary gate, by the back floating potential or by the combination of both. This feature allows for the control of the on‐voltage of the transistors, from depletion to enhancement mode, for instance. Moreover, this specific characteristic allows the implementation of universal logic gates (NAND and NOR) using only one transistor, by setting the proper combination of the voltage level applied at each gate. This way a simple and universal device architecture can be envisaged towards the simplification of the production of low power electronic systems on paper.

Keywords

• dual‐gate oxide‐based field effect transistors
• paper electronics
• paper transistors
• universal logic gates