Ultra-Low-Voltage UTBB-SOI-Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications

Abstract

Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can be leveraged to realize high-performance CMOS circuits. However, an ultra-low-voltage operation is necessary to minimize the power consumption and to offset the cooling cost overheads. The MOSFET threshold voltages (Vt) increase at cryogenic temperatures making it challenging to achieve high performance while operating at very low voltage. Ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)-based MOSFETs can modulate the transistor threshold voltage using the back-gate bias, unlike conventional FinFETs. This unique UTBB-SOI technology attribute has been leveraged to realize compact pseudo-static storage circuits, namely, embedded dynamic random access memory (DRAM) bitcell and a flip-flop operating at 0.2 V and 77 K. This article presents UTBB-SOI device fabrication details and calibrate experimental device characteristics with BSIM compact models. SPICE simulations suggest the feasibility of three-transistor gain-cell embedded DRAM (eDRAM) capable of reliably storing three distinct voltage levels (1.5 bits/cell) and exhibiting retention time of the order of 104 s. Furthermore, a unique pseudo-static flip-flop design is presented, which can lower the clock power by 50%, transistor count by 20%, and static power consumption by 20%.

Keywords

• Cryo-CMOS
• embedded dynamic random access memory (eDRAM)
• flip-flop
• pseudo-static
• retention time
• ultra-thin body and buried oxide silicon-on-insulator (UTBB-SOI)