A Hardware-Accelerated Approach to Chaotic Image Encryption: LTB Map and FPGA Implementation

Abstract

The need for high-speed and secure image encryption has become increasingly critical in the digital age, driven by the rapid growth of digital data, the rapid advancement of internet technologies, and the limitations of traditional encryption algorithms. This paper addresses this need by proposing a novel high-speed and secure image encryption that leverages the flexibility and parallelism of Field-Programmable Gate Arrays (FPGAs). Firstly, we present the LTB map, an enhanced chaotic map that synergistically combines three distinct 1D chaotic maps (the Logistic, Tent, and Bernoulli shift maps) into a single framework. The resulting LTB map exhibits an expanded key space and a heightened level of complexity and unpredictability compared to its constituent maps operating independently. Furthermore, the LTB map adopts a 32-bit fixed-point representation and involves simple operations like addition, subtraction, and multiplication, resulting in a resource-efficient implementation on FPGA platform. Additionally, we propose a new image encryption algorithm based on the LTB map. The LTB map plays a pivotal role in scrambling pixel values and positions during the confusion and diffusion operations, thereby ensuring robust security. By leveraging the inherent parallelism of the LTB map and parallelizing encryption operations, coupled with efficient hardware implementation on FPGAs, our encryption method achieves high-speed performance while maintaining strong security properties.

Keywords

• FPGA implementation
• chaotic maps
• LTB map
• high-speed image encryption