22 nm SRAM Design for Ultra-Low Power (ULP) Applications

Abstract

Nanotechnology has become a rapidly growing field with potential low power applications, that emerging the challenge of the power management. In portable devices, static random-access memories (SRAM) circuits can significantly contribute to the total power consumption especially in the standby mode due to the increase effects of leakage currents which impact the system performance and functionality. Therefore, designing SRAM circuits consuming low power dissipation is in a high demand. The sleepy stack technique is the effective technique that acting efficiently on power dissipation reduction for enabling the operation of SRAMs in ultra-lowpower (ULP) applications. In this paper, a new sleepy stack technique is proposed for the 8-transistor (8T) SRAM design to limit the impact of static power consumption for ULP applications using advanced technology nodes of 22 nm lithography. It performs a better performance, cost savings, and has great compatibility and stabilization with portable systems. Spice simulation package is used to validate the theoretical fundamentals and basics. Results show satisfactory outcomes as an efficient feasible solution for portable devices and ULP applications, and thereby it supposed to be applied for a system with long-term passive periods with a highspeed response time requirement.

Keywords

• 22 nm sram
• ultra-low power (ulp) applications
• sleepy stack technique