Minimization of DC-Link Capacitance and Improved Operational Performance of a 5-Level Hybrid Multilevel DC-Link Inverter

Abstract

This study analyzes a single-phase hybrid multilevel dc-link (MLDCL) inverter, in which a dc-link with two capacitors is integrated into a single dc source. When controlled under the conventional modulation scheme, the MLDCL inverter synthesizes a five-level output voltage. As the capacitor-voltage balancing depends on the fundamental period, the output voltage may contain unsolicited low-order harmonics. Moreover, in the conventional scheme, this inverter requires large dc-link capacitors. To avoid these problems, the present paper develops a simple phase-shifted pulse-width modulation scheme based on redundant switching states, which controls the MLDCL inverter and balances the capacitor voltage within each carrier period. The proposed modulation scheme also minimizes the dc-link capacitance by a factor of the frequency modulation ratio while reducing the total harmonic distortion of the output voltage and current. Unlike the conventional method, the proposed scheme considerably reduces the capacitor-voltage ripples and can be regulated by increasing the carrier frequency, thereby reducing the voltage stress on the switches and improving the reliability of the inverter. The feasibility of the proposed scheme over the conventional scheme is confirmed in a comparative study. Finally, the steady-state and dynamic performances of the proposed strategy are demonstrated in simulations and validated in experiments.

Keywords

• H-bridge
• H6D2
• 5-level inverter
• multilevel dc-link (MLDCL) inverter
• minimization of capacitance
• phase-shifted PWM