IEEE Open Journal of the Solid-State Circuits Society (Jan 2024)

A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

  • Linsheng Zhang,
  • Divya Duvvuri,
  • Suprio Bhattacharya,
  • Anjana Dissanayake,
  • Xinjian Liu,
  • Henry L. Bishop,
  • Yaobin Zhang,
  • Travis N. Blalock,
  • Benton H. Calhoun,
  • Steven M. Bowers

DOI
https://doi.org/10.1109/OJSSCS.2024.3387388
Journal volume & issue
Vol. 4
pp. 43 – 56

Abstract

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This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2– $171~\mu $ A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.

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