Design of 7T SRAM Using InGaAs-Dual Pocket-Dual Gate-Tunnel FET for IoT Applications

Abstract

The Internet of Things (IoT) is becoming increasingly popular in areas like wearable communication devices, biomedical devices, and home automation systems. IoT-compatible processors or devices need larger integrated memory circuits, like static random access memory (SRAM). The design of such a larger memory with fast access times and low leakage is a challenge. This article proposes a 7T SRAM cell using an InGaAs-dual pocket-dual gate-tunnel FET (InGaAs-DP-DG-TFET) device. We have compared the key metrics of SRAM, such as read/write delay, stability, and power consumption, with 7T SRAM based on existing TFET devices. The 7T cell designed in this work significantly improved read and write access times. The proposed SRAM shows a decrement of read delay (write delay) by approximately 10x (210x) and 2.5x (43x) times compared to the 7T SRAM cell implemented using Si-DP-DG-TFET and InGaAs/Si-DP-DG-TFET at $V_{DD}$ = 700 mV. The proposed cell has the highest write margin (WM) and the least leakage power compared to the other cells examined here. The WM of the proposed 7T SRAM cell is 5x and 1.6x higher at $V_{DD}$ = 500 mV, compared to Si-DP-DG-TFET and InGaAs/Si-DP-DG-TFET counterparts, respectively. We computed the leakage power of the 7T SRAM cell since it is an essential factor in the design of SRAM. To explore the performance of TFET-based SRAM operation, we have carried out circuit simulations at various supply voltages and for different cell sizes. These simulations also offered an assessment of the cell’s dynamic performance. We employed a Verilog-A-based lookup table technique and ran simulations in the commercial HSPICE circuit simulator. The low leakage power and fast memory access of the proposed cell make it a promising candidate for IoT applications.

Keywords

• Access time
• device-circuit
• InGaAs
• leakage power
• lookup table approach
• mixed-mode