Compact pattern set generation for accelerated small delay defect testing

Abstract

Faster-than-at-speed testing (FAST) approach significantly enhances the detection quality of small delay defects (SDD). However, it encounters the challenge of an increased number of test options. Also, selecting the optimal test clock periods is crucial to prevent test escapes and avoid overtesting the circuit. This paper presents a state-of-the-art test clock data set-based feedback-driven clock selection algorithm to enhance quality while maintaining a compact pattern set with fewer test clock periods. The algorithm's advantages become apparent when combined with an appropriate base pattern repository. For this purpose, the proposed method employs various combinations of timing-aware (TA) patterns, topped off with transition delay fault (TDF) patterns. The effectiveness of the proposed framework is validated by generating the test options that maximize the Weighted Slack Percentage (WeSPer) quality metric using a test optimization technique. The technique was validated using the ISCAS89 and ITC99 benchmark circuits. It exhibited a superior performance by reducing the pattern count to approximately 2x times the TDF patterns with a reduced number of test clock periods. Additionally, it achieved a 100% utilization of the selected test clock periods, while incurring only a maximal WeSPer loss of 0.15%.

Keywords

• Faster-than-at-speed testing
• Delay fault models
• Small delay defects
• Nanoscale devices
• Test quality metric
• VLSI testing