A timely switch fault ride-through method for VSC-HVDC system

Abstract

In order to achieve the fault through of voltage source converter-based high voltage direct current (VSC-HVDC)system during alternating current (AC) system asymmetric faults and keep stability of the impedance at steadystate, a timely switch fault through method for VSC-HVDC system is proposed in this paper. Firstly, the positive and neg-ative sequence control of VSC-HVDC system and the effect of decomposition algorithm with 1/4 cycle delay on the impedance of VSC-HVDC system are analyzed. The high frequency impedance model on the AC side of VSC-HVDC system established. Then, on this basis, the AC fault is judged by the steady-state quantity and ab-rupt quantity of negative sequence voltage. In the steady state, the full sequence current control without positive and negative sequence decomposition is used to reduce the periodic fluctuation of the VSC-HVDC system impedance. In the transient state of fault, the negative sequence current control is superimposed to suppress the negative sequence fault current and realize the continuous operation of the system. Finally, model of VSC-HVDC system is developed in PSCAD/EMTDC to prove the validity of the proposed control method.

Keywords

• voltage source converter-based high voltage direct current (vsc-hvdc)
• fault ride-through
• positive and negative sequence decomposition
• vsc-hvdc system impedance
• full sequence current control
• unbalance fault