Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers

Abstract

A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions.

Keywords

• Digital delta-sigma modulator (DDSM)
• fractional-N phase-locked loop (PLL)
• frequency synthesizer
• nonlinearity