A Compact and Low Latency SPM Architecture for ECC Cryptosystems

Abstract

Elliptic curve cryptography (ECC) is largely deployed public key cryptographic algorithms in the design of key exchange, digital signature, and secure multiparty computation protocols. A compact and high-performance implementation of ECC is essential to enable deployments of associated protocols in privacy-preserving applications. Scalar point multiplication (SPM), the chief and performance-limiting primitive in ECC is computationally intensive. To speed up the computation of SPM with low resource consumption, this paper presents ComCrypt, a novel compact and low latency hardware architecture over any generic prime field. The proposed design features new novel unified hardware architectures for low-level finite field arithmetic primitives. These architectures are developed by introducing optimization both at algorithmic and circuit levels. In these basic primitives, parallelism opportunities are exploited at the algorithmic level to increase the achievable frequency, whereas, a novel resource-sharing strategy is deployed to reduce the hardware cost at the circuit level. Due to these efforts, the proposed SPM design produces better area-time product and efficiency results. It is implemented on Xilinx Virtex-7, Kintex-7, and Virtex-6 FPGA platforms for 256-bit modulus length. It significantly improves latency and resource consumption compared to the existing ECC-based hardware accelerators.

Keywords

• Scalar point multiplication
• Montgomery ladder
• elliptic curve cryptography (ECC)
• FPGA implementation
• arithmetic circuits for finite fields