Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs

Abstract

Quantum error correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the NN for the high-decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware-based NN-decoders can achieve the high-decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements $(\approx 440\ \text{ns})$ of current solid-state qubit technologies for both application-specific integrated circuit designs $(< \!30\ \text{ns})$ and field-programmable gate array implementations $(<\! 90\ \text{ns})$. These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.

Keywords

• Application-specific integrated circuit (ASIC)
• complementary metal-oxide semiconductor (CMOS)
• CMOS integrated circuits
• combinational circuits
• cryo-CMOS decoding
• cryogenic electronics