An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

Abstract

This article presents a novel approximate adder that is design-optimized and has optimized error metrics. Optimization in design translates into optimization of the design parameters such as delay, power, and area/resources, and optimization of the error metrics points to the usefulness of the proposed approximate adder for practical applications. We refer to the proposed approximate adder that is hardware optimized and having a near-normal error distribution as HOAANED, in short. We consider the implementation of HOAANED and the other approximate adders based on ASIC and FPGA design environments. We used a Xilinx Artix-7 device for a FPGA implementation, and a 32/28-nm CMOS standard digital cell library for an ASIC based implementation. To demonstrate the practical utility of HOAANED, we considered digital image processing as a practical application and performed experimentation with many images. The quality of the images reconstructed using the approximate adders was analyzed based on the peak signal-to-noise ratio (PSNR), which is used as a qualitative figure-of-merit to assess the images. It is found that HOAANED achieves an improved PSNR in comparison with the other approximate adders for image processing, and this is achieved with HOAANED simultaneously featuring optimized design metrics and error characteristics.

Keywords

• Adders
• approximate computing
• digital circuits
• high speed
• logic design
• low power