A 19 ps Precision and 170 M Samples/s Time-to-Digital Converter Implemented in FPGA with Online Calibration

Abstract

This paper presents a 19 ps precision and 170 M samples/s time-to-digital converter (TDC) in FPGA. Through the direct count method and tapped delay line method, the coarse count and fine count can be extracted, respectively. The direct count is realized by the 350 M clock and the tapped delay line is constructed by the CARRY4 block. The ones-counter encoder is used to convert the thermometer code with bubble errors into binary code, which is applicable to all the FPGA chips. This work not only explains the schematic of the ones-counter encoder, but also shows how to configure it. Owing to the inconsistency of delay elements caused by process, bin-by-bin calibration is utilized to improve the differential nonlinearities (DNL) and integral nonlinearities (INL) of the TDC. A novel method was developed to compensate the influence of voltage and temperature. As the delay elements vary with voltage and temperature, a frequency counter is used to extrapolate and compensate its effect on the delay line. All of the above strategies use online calibration and improve the precision and sampling rate of TDC. The experimental results show the least significant bit (LSB) achieves 17.4 ps, the DNL is within [−0.90, 1.67] LSB, and the INL is in the range of [−1.90, 3.31] LSB.

Keywords

• time-to-digital converter
• FPGA
• tapped delay line
• bubbles
• online calibration