Моделирование и анализ информационных систем (Oct 2016)

On Numerical Characteristics of а Simplex and their Estimates

  • M. V. Nevskii,
  • A. Yu. Ukhalov

DOI
https://doi.org/10.18255/1818-1015-2016-5-603-619
Journal volume & issue
Vol. 23, no. 5
pp. 603 – 619

Abstract

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Let \(n\in {\mathbb N}\), and let \(Q_n=[0,1]^n\) be the \(n\)-dimensionalunit cube. For a nondegenerate simplex \(S\subset {\mathbb R}^n\), by\(\sigma S\) we denote the homothetic image of \(S\)with the center of homothety in the center of gravity of S and theratio of homothety \(\sigma\). We apply the followingnumerical characteristics of the simplex.Denote by \(\xi(S)\) the minimal \(\sigma>0\) with the property\(Q_n\subset \sigma S\). By \(\alpha(S)\) we denote the minimal\(\sigma>0\) such that \(Q_n\) is contained in a translateof a simplex \(\sigma S\).By \(d_i(S)\) we mean the \(i\)th axial diameter of \(S\), i.\,e.the maximum length of a segment contained in \(S\) and parallelto the \(i\)th coordinate axis. We apply the computationalformulae for\(\xi(S)\), \(\alpha(S)\), \(d_i(S)\) which have been proved by the firstauthor. In the paper we discuss the case \(S\subset Q_n\).Let\(\xi_n=\min\{ \xi(S): S\subset Q_n\}. \)Earlier the first author formulated the conjecture:{\it if\(\xi(S)=\xi_n\), then \(\alpha(S)=\xi(S)\).} He proved this statementfor \(n=2\) and the case when \(n+1\) is an Hadamard number, i.\,e.there exists an Hadamard matrix of order \(n+1\). The followingconjecture is a strongerproposition: {\it for each \(n\),there exist \(\gamma\geq 1\), not depending on \(S\subset Q_n\), such that\(\xi(S)-\alpha(S)\leq \gamma (\xi(S)-\xi_n).\)}By \(\varkappa_n\) we denote the minimal\(\gamma\) with such a property.If \(n+1\) is an Hadamard number, then the precise value of \(\varkappa_n\)is 1. The existence of \(\varkappa_n\) for other \(n\)was unclear. In this paper with the use of computer methods we obtainan equality$$\varkappa_2 = \frac{5+2\sqrt{5}}{3}=3.1573\ldots $$Also we prove a new estimate$$\xi_4\leq \frac{19+5\sqrt{13}}{9}=4.1141\ldots,$$which improves the earlier result \(\xi_4\leq \frac{13}{3}=4.33\ldots\)Our conjecture is that \(\xi_4\) is precisely\(\frac{19+5\sqrt{13}}{9}\). Applying this valuein numerical computations we achive the value$$\varkappa_4 = \frac{4+\sqrt{13}}{5}=1.5211\ldots$$Denote by \(\theta_n\) the minimal normof interpolation projection on the space of linear functions of \(n\)variables as an operator from\(C(Q_n)\)in \(C(Q_n)\). It is known that, for each \(n\),$$\xi_n\leq \frac{n+1}{2}\left(\theta_n-1\right)+1,$$and for \(n=1,2,3,7\) here we have an equality.Using computer methods we obtain the result \(\theta_4=\frac{7}{3}\).Hence, the minimal \(n\) such that the above inequality has a strong formis equal to 4.%, a principal architecture of common purpose CPU and its main components are discussed, CPUs evolution is considered and drawbacks that prevent future CPU development are mentioned. Further, solutions proposed so far are addressed and new CPU architecture is introduced. The proposed architecture is based on wireless cache access that enables reliable interaction between cores in multicore CPUs using terahertz band, 0.1-10THz. The presented architecture addresses the scalability problem of existing processors and may potentially allow to scale them to tens of cores. As in-depth analysis of the applicability of suggested architecture requires accurate prediction of traffic in current and next generations of processors we then consider a set of approaches for traffic estimation in modern CPUs discussing their benefits and drawbacks. The authors identify traffic measurements using existing software tools as the most promising approach for traffic estimation, and use Intel Performance Counter Monitor for this purpose. Three types of CPU loads are considered including two artificial tests and background system load. For each load type the amount of data transmitted through the L2-L3 interface is reported for various input parameters including the number of active cores and their dependences on number of cores and operational frequency.

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