A gate driver for parallel connected MOSFETs with crosstalk suppression

Abstract

New semiconductor materials offer several advantages for modern power systems, including low switching and conduction losses, excellent thermal conduction of a die, and high operation temperature. Avionics is one of the main beneficiaries of the progress in power devices, as it enables more compact and lighter converters for future More Electrical Aircraft. However, these advancements also come with new challenges that must be addressed to avoid potentially dangerous situations and fully utilize the capabilities of fast SiC MOSFETs. One such challenge is the high drain voltage rate during the switching process, which leads to a significant injection of current into the gate circuit (crosstalk effect). This increased current injection increases the risk of shoot-through conduction and thermal runaway. Although preventive measures are well-known, they offer limited protection in the case of parallel MOSFET connections. Therefore, this paper considers crosstalk features for parallel MOSFET connections, such as parasitic inductance of gate driver trace and gate voltage distribution. A special model is proposed to predict the magnitude of induced gate voltage under different conditions considering the nonlinear behavior of the MOSFET reverse capacitance. A new clamp circuit with an individual low-inductance path for each parallel switch is also proposed to suppress the consequences of crosstalk. The modified circuit operates independently from the main gate driver circuit; therefore, it does not change the switching time and electromagnetic interference pattern of the inverter. The efficiency of the new gate driver is confirmed through simulation and experimental results.

Keywords

• power electronics
• sic mosfet
• parallel connection
• gate driver
• parasitic effects