A three‐stage switching MMC topology for capacitor voltage ripple reduction in HVDC applications

Abstract

Abstract Modular multi‐level converters (MMCs) are a mainstay in many HVDC transmission projects worldwide. Half‐bridge MMC (HB‐MMC) is mostly used in the current project. The large capacitor of sub modules (SMs) is often required in MMC to ensure the low voltage ripple. Here, the three‐stage switching MMC (TSS‐MMC) topology is proposed, which can greatly reduce the capacitor voltage ripple of SMs by dynamically adjusting the position of inductance on the upper and down bridge arms. The principle of reducing capacitor voltage ripple based on equal capacitance theory is introduced. The selection of the inductance value of each part in TSS‐MMC is introduced. The start‐up process strategy, capacitor voltage ripple reduction strategy in steady‐state operation, and DC fault ride‐through strategy of TSS‐MMC are proposed. The effectiveness and engineering practicability of the proposed TSS‐MMC is verified by transient simulation program built on PSCAD/EMTDC. The simulation results show that compared with MMC with circulating current suppressing controller (CCSC), it can effectively reduce the capacitor voltage ripple by over 50%. Furthermore, the total used inductance of TSS‐MMC can also be reduced. A comprehensive assessment of TSS‐MMC is also carried out.

Keywords

• HVDC power convertors
• HVDC power transmission
• power system simulation
• power system transients