Vertical Surrounding Gate Transistor for High Density and Low Voltage Operation in DRAM

Abstract

In this article, a honeycomb vertical surrounding gate access transistor array scheme is proposed to further decrease the DRAM cell area with aggressively shrink bit line (BL) pitch and word line (WL) pitch adopting the ZigZag BL and WL air gap. To verify the process feasibility, process flow emulation is optimized by virtual fabrication with SEMulator3D®. Moreover, the ZigZag BL feasibility in lithography process is evaluated by optical proximity correction (OPC) simulation. In addition, the parasitic capacitance of BL and WL decrease 22.8% and 76.8%, respectively, as compared to reference paper. And the electrical properties of the proposed device are simulated by three-dimensional technology computer aided design (3D TCAD). The GIDL effect is prohibited through prolonging the drain extension and reducing its doping concentration. Finally, the surrounding gate transistor can achieve high on-state current ( $30~\mu \text{A}$ ) at $\text{V}_{\mathrm {g}}=1.5$ V and off-state current below 0.1 fA at $\text{V}_{\mathrm {d}}= -0.2$ V. These results are beneficial for the direction of pathfinding for increasing the density and decreasing the energy consumption of DRAM.

Keywords

• Vertical surrounding gate transistor (VSGT)
• dynamic random-access memory (DRAM)
• parasitic capacitance
• optical proximity correction (OPC)
• area scaling
• power saving