Efficient adders for assistive devices

Abstract

The Body sensor network [IEEE 802.15] is a wireless communication network consisting of assistive devices which are of prime importance in medical applications. The delay critical and power hungry blocks in these assistive devices are designed so that they consume less power, have low latency and require a lesser area on chip. In this paper, we present a qualitative as well as a quantitative analysis of an asynchronous pipelined adder design with two latest computation completion sensing approaches based on Pseudo NMOS logic and other based on C-element. The Pseudo NMOS based completion sensing approach provides a maximum improvement of 76.92% in critical path delay at supply voltage of 1.2 V and the maximum drop in power dissipation has been observed at a supply voltage of 1.1 V which is 85.60% as compared to C-element based completion sensing approach. Even at low voltages such as 0.8 V, there is a significant improvement in speed and power which is 75.64% and 74.79% respectively. Since the adder is the most widely used component in all present day assistive devices, this analysis acts as a pointer for the application of asynchronous pipelined circuits with efficient Pseudo NMOS based completion sensing approach in low voltage/low power rehabilitative devices.

Keywords

• BANs-Body Area Networks
• Body sensor networks
• CSC-completion sensing circuit
• CB-computational block
• DUT-device under test
• Domino CMOS logic