Results in Engineering (Jun 2024)

An inspired chaos-based estimation-theory optimization for low-density parity-check (LDPC) code decoding

  • Fadl Dahan, Ph.D,
  • Michaelraj Kingston Roberts,
  • Munivenkatappa Nagabushanam, Ph.D,
  • Taha M. Alfakih, Ph.D

Journal volume & issue
Vol. 22
p. 101986

Abstract

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Optimization techniques have emerged as powerful tools for solving complex engineering problems in real-time applications, surpassing traditional heuristic methods. This paper introduces a novel chaos optimization algorithm that integrates the bisection search method to enhance the convergence ability, solution accuracy, and search speed of conventional optimization problems. The proposed algorithm is applied to the design and analysis of a reduced complexity decoding scheme using Low-Density Parity-Check (LDPC) codes. By leveraging the Linear Minimum Mean Square Error (LMMSE) estimation criterion, the proposed method approximates the estimated parameters acquired during the message computation process. This combined approach effectively mitigates error propagation and premature convergence issues. The presented research offers a low-complexity decoding algorithm for LDPC codes, leveraging an optimized chaos bisection search method. The adoption of the LMMSE criterion overcomes data dependency and error propagation concerns during the estimation process. The modified chaos optimization technique, integrated with the bisection search, efficiently determines optimal values from perturbed observations, leading to improved convergence rates and data processing precision by reducing the observation dimension (search space). Simulation results validate the proposed approach, showcasing its ability to mitigate error propagation and premature convergence while maintaining coding gain accuracy. Experimental validation on an FPGA RF-SoC device (model XCZU27DR) demonstrates that the proposed method achieves a maximum throughput of 8.7 Gbps at a clock frequency of 386.72 MHz, with reduced hardware complexity. The experimental verification on an FPGA RF-SoC device highlights the algorithm's minimal hardware complexity, superior decoding throughput, and Bit Error Rate (BER) performance.

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