Fabrication and Electrical Characterization of High Aspect Ratio Through-Silicon Vias with Polyimide Liner for 3D Integration

Abstract

High aspect ratio (HAR) through-silicon vias (TSVs) are in urgent need to achieve smaller keep-out zones (KOZs) and higher integration density for the miniaturization of high-performance three-dimensional (3D) integration of integrated circuits (IC), micro-electro-mechanical systems (MEMS), and other devices. In this study, HAR TSVs with a diameter of 11 μm and an aspect ratio of 10:1 are successfully fabricated in a low-cost process flow. Conformal polyimide (PI) liners are deposited using a vacuum-assisted spin coating technique, and the effects of spin coating time and speed on the deposition results are discussed. Then, continuous Cu seed layers are fabricated by sequential sputtering and ultrasound-assisted electroless plating. Additionally, void-free and seamless Cu conductors are formed by electroplating. Moreover, a semi-additive method is used to fabricate the redistribution layers (RDLs) on the insulating layers of photosensitive PI (PSPI). Notably, a plasma bombardment process is introduced to remove residual PSPI in the contact windows between RDLs and central pillars. Results show that the resistance of a single TSV from a daisy chain of 144 TSVs with density of 2000/mm2 is about 28 mΩ. Additionally, the S-parameters of a single TSV are obtained using L-2L de-embedding technology, and the experimental and simulated results agree well. The proposed low-cost fabrication technologies and the related electrical characterization of PI-TSVs are significant for the application of HAR TSVs in modern heterogeneous integration systems.

Keywords

• three-dimensional (3D) integration
• high aspect ratio (HAR) through-silicon vias (TSVs)
• polyimide (PI) liner
• Cu seed layer
• redistribution layers (RDLs)
• S-parameters