IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (Jan 2021)
Characterization and Modeling of 22 nm FDSOI Cryogenic RF CMOS
Abstract
Analog and RF mixed-signal cryogenic-CMOS circuits with ultrahigh gain-bandwidth product can address a range of applications such as interface circuits between superconducting (SC) single-flux quantum (SFQ) logic and cryo-dynamic random-access memory (DRAM), circuits for sensing and controlling qubits faster than their decoherence time for at-scale quantum processor. In this work, we evaluate RF performance of 18 nm gate length ( $L_{G}$ ) fully depleted silicon-on-insulator (FDSOI) NMOS and PMOS from 300 to 5.5 K operating temperature. We experimentally demonstrate extrapolated peak unity current-gain cutoff frequency ( $f_{T}$ ) of 495/337 GHz ( $1.35\times /1.25\times $ gain over 300 K) and peak maximum oscillation frequency ( $f_{\mathrm {MAX}}$ ) of 497/372 GHz ( $1.3\times $ gain) for NMOS/PMOS, respectively, at 5.5 K. A small-signal equivalent model is developed to enable design-space exploration of RF circuits at cryogenic temperature and identify the temperature-dependent and temperature-invariant components of the extrinsic and the intrinsic FET. Finally, performance benchmarking reveals that 22 nm FDSOI cryogenic RF CMOS provides a viable option for achieving superior analog performance with giga-scale transistor integration density.
Keywords
