Verification of power hardware-in-the-loop environment for testing grid-forming inverter

Abstract

Grid-forming inverters (GFMIs) are promising technologies that can replace some of the capabilities traditionally provided by synchronous generators (SGs), such as inertial response. While there have been many simulation-based studies on GFMIs, performance testing has not been adequately discussed. Power hardware-in-the-loop (PHIL) simulation is an attractive option for testing GFMIs. The interaction between GFMI and power systems can be observed under a variety of conditions, including low-inertia and contingency conditions. Since PHIL testing was primarily used for grid-following inverters (GFLIs), the PHIL configuration needs to be adjusted to test GFMIs, which respond faster to changes in grid voltage than GFLIs. This paper proposes the PHIL setup for testing GFMIs. It utilizes the PHIL interface developed for testing GFLIs and adjusts it for testing GFMIs. The stability and accuracy of the PHIL testing are evaluated in terms of frequency stability in low-inertia power systems by comparing test and simulation results.

Keywords

• Power hardware-in-the-loop
• Grid-forming inverter
• Low-inertia power system
• Frequency stability
• Rate of change of frequency
• Frequency nadir