Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation

Abstract

Neural compact models are proposed to simplify device‐modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy and speed, which limits their usefulness in multi‐device applications and reduces the quality of circuit simulations. To address these drawbacks, a neural compact modeling framework with a flexible selection of technology‐based model parameters using a two‐stage neural network (NN) architecture is proposed. The proposed neural compact model comprises two NN components: one utilizes model parameters to program the other, which can then describe the current–voltage (I–V) characteristics of the device. Unlike previous neural compact models, this two‐stage network structure enables high accuracy and fast simulation program with integrated circuit emphasis (SPICE) simulation without any trade‐off. The I–V characteristics of 1000 amorphous indium–gallium–zinc‐oxide thin‐film transistor devices with different properties obtained through fully calibrated technology computer‐aided design simulations are utilized to train and test the model and a highly precise neural compact model with an average IDS error of 0.27% and R2 DC characteristic values above 0.995 is acquired. Moreover, the proposed framework outperforms the previous neural compact modeling methods in terms of SPICE simulation speed, training speed, and accuracy.

Keywords

• compact models
• machine learnings
• neural networks
• technology computer‐aided designs
• transistors