Exploiting CMOS Manufacturing to Reduce Tuning Requirements for Resonant Optical Devices

Abstract

We present manufacturing tolerances of cascaded silicon microring resonators fabricated in a commercial 130-nm complementary-oxide semiconductor (CMOS) foundry using 193-nm lithography and provide statistics gathered from over 500 four-channel microring arrays over multiple wafers and fabrication lots. We quantify intrawafer and interwafer variation of the position and relative spacing of resonance wavelengths for the microring arrays and confirm prior predictions that the absolute resonance positions of such devices cannot be controlled across wafers or even across reticles within a wafer. However, we show that the free spectral range (FSR) of the microrings can be controlled to within 0.66 nm (83 GHz) across wafers and lots, as can the wavelength spacing between closely spaced microrings. To exploit these findings for low-power optical interconnects, we suggest and demonstrate a synthetic resonant comb with $FSR \approx N\ast \delta\lambda$, wherein resonance wavelengths are spaced equally across the FSR in order to minimize postfabrication tuning. The experimental CMOS 1 $\times$ 8 microring array requires an average tuning of less than 1.2 nm/channel to align to a 200-GHz wavelength division multiplexing (WDM) grid. Monte Carlo simulations on 100 000 sample runs show that an average tuning of 1.72 nm/channel is sufficient for 99% coverage for this component. This indicates that it is possible, with high statistical confidence, to use high-volume CMOS manufacturing to reduce the tuning range and tuning energy requirements of silicon microrings and, hence, enhance their ability to be used in high-density, energy-efficient computing system applications.

Keywords

• Silicon nanophotonics
• optical interconnects
• technologies for computing