A 4.56 Gbps/Lane MIPI C-PHY Transmitter With Boosting Pre-Driver

Abstract

This paper describes the development of a Mobile Industry Processor Interface (MIPI) C-PHY transmitter (TX) fabricated using a 28-nm CMOS process with a 1 V supply. In its operational mode, the TX effectively converted parallel signals into low-voltage and high-speed tri-level signals, facilitating seamless serial data transmission. A key aspect of the proposed TX design was the integration of an equalizer (TxEQ) capable of implementing de-emphasis to mitigate channel-induced inter-symbol interference, thereby ensuring robust high-speed data transmission. Furthermore, the output driver was meticulously designed with an optimized structure to ensure impedance matching in different operating modes. Remarkably, the introduction of a boosting pre-driver further enhanced the driving capability, operating independently from the TxEQ of the output driver. Each lane occupied an area of 0.284 mm2, accommodating necessary components such as a pseudo-random bit sequence for random data generation. By employing a boosting technique, the TX achieved a commendable power efficiency of 1.21 mW/Gbps/lane while simultaneously delivering a remarkable 0.52 UI eye-opening at a data transfer rate of 4.56 Gbps/lane.

Keywords

• C-PHY transmitter
• mobile industry processor interface
• boosting pre-driver
• driver circuit
• impedance matching