SRAM Design Issues and Effective Panacea at Different CMOS Technology Nodes

Abstract

This brief introduces the solutions for different design issues in a 6T static random-access memory (SRAM) cell. In this paper an overview of conventional 6T SRAM cell and its limitations are discussed. Then there is a brief discourse for SRAM cell design issues for different technology node. The SNM was examined and it was found that 7T SRAM possess better RSNM & WSNM as compared to other designs. Since there is only 0.4m2 increase in area it would not be a problem so overall stability is high. 5T possess better leakage power due to reduce in almost 94% of it along with reducing the area so maintaining area overhead problems.

Keywords

• static random-access memory (sram)
• leakage power
• static noise margin (snm)