A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS

Abstract

This paper presents a 12-bit 1.1GS/s single-channel pipelined-successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) with a three-stage architecture implemented in a 28nm CMOS technology. A new technique that provides adaptive inter-stage redundancy is proposed to mitigate the speed overhead of the conventional inter-stage redundancy bit. An adaptive inter-stage redundancy bit is implemented in the third stage to improve its conversion speed. In addition, the first-stage CDAC is implemented with a large-DAC and a small-DAC to address the speed bottleneck by improving the settling speed during the bit conversions, and a high speed detect-and-skip (DAS) decoder with minimum power overhead is incorporated to reduce the switching power without affecting the high-speed operation. The single-channel ADC achieves an SNDR of 60.1 dB and an SFDR of 75.3 dB at the Nyquist input operating at 1.1GS/s. With 8.5 mW power consumption at a 0.9 V power supply, it achieves a Walden FOM of 9.3 fJ/conv.-step and a Schreier FOM of 168.2 dB.

Keywords

• Analog-to-digital converter (ADC)
• successive approximation register (SAR)
• pipelined-SAR ADC
• inter-stage redundancy
• DAC switching