IEEE Access (Jan 2024)

Enhancing High-Speed Data Communications: Optimization of Route Controlling Network on Chip Implementation

  • P. Anuradha,
  • Pratham Majumder,
  • Kanithan Sivaraman,
  • N. Arun Vignesh,
  • S. Arun Jayakar,
  • Anthoniraj Selvaraj,
  • Saurav Mallik,
  • Amal Al-Rasheed,
  • Mohamed Abbas,
  • Ben Othman Soufiene

DOI
https://doi.org/10.1109/ACCESS.2024.3427808
Journal volume & issue
Vol. 12
pp. 123514 – 123528

Abstract

Read online

In the paradigm of Device-to-Device (D2D) and System-on-Chip (SoC) communications, the optimization of high-speed data transfer while minimizing hardware resource utilization imposing paramount importance. Traditional methodologies have often resulted in undesirable outcomes, such as inflated area, latency, and power consumption. Consequently, this study adopts a focused approach by introducing an innovative Route-Controlling Network-on-Chip (RC-NoC) architecture, integrating critical components like FIFO-Buffer, crossbar switching, route control, and arbiter modules. The operational sequence begins with the FIFO-Buffer logic, which strategically manages data storage from diverse devices, allocating and organizing data flow based on distinct IP addresses. Subsequently, the route controller module orchestrates the operation of heterogeneous routers within the crossbar switching fabric, implementing a prioritized scheduling scheme. The arbiter plays a crucial role in overseeing and directing data flow from source to destination, leveraging request-level prioritization for efficient data transmission. Empirical evidence from simulations unequivocally demonstrates the superiority of the proposed RC-NoC architecture. Comparative analysis against essential state-of-the-art NoC architectures reveals significant enhancements in key metrics, notably area efficiency, latency reduction, and power optimization, with over 45% improvement observed across these metrics compared to GALS-NoC, F-NoC, and CE-NoC in the Orion framework. This robust validation substantiates the efficacy and technical prowess of the RC-NoC design paradigm in addressing the challenges of modern D2D and SoC communication paradigms. Furthermore, the optimization process notably decreased routing costs for different packets, with Router2 exhibiting a 40% reduction in Packet1’s routing cost and Router3 displaying a 44% decrease in Packet2’s cost. Moreover, the attained router capacities demonstrated an average increase of 17%, significantly enhancing network efficiency.

Keywords