A time latch for high speed time‐based ADCs

Abstract

Abstract This letter presents a novel time latch for high speed time domain analogue to digital converters. The time latches reported in literature suffer from a limited maximum operating frequency, which makes them unsuitable for high frequency applications. Analysis of the proposed time latch shows it can operate at 10 GHz, 2.5x higher than the best reported time latch. Furthermore, simulations in 28 nm CMOS technology confirm that the enhancement in the speed of the proposed time latch comes with low overhead in area and power. Potential design issues with the proposed time latch are also discussed.