Synchronisation of a distributed control and data acquisition system for modular multi-level PHIL amplifiers

Abstract

This research presents a novel technique to synchronise a modular control and data acquisition system for the testing of multi-level power hardware-in-the-loop (PHIL) amplifiers. The methodology is inspired by the precision timing protocol, used to compensate for communications latency between distributed control nodes. It uses a non-conventional digital pulse-width modulation (PWM) technique, phase accumulator carrier pulse-width modulation to achieve carrier synchronisation across the system. A prototype design has been demonstrated on a three-node test bench, showing single clock cycle (10 ns) precision when synchronising a 25 kHz PWM carrier wave, with minimal sensitivity to communications link propagation delays.

Keywords

• synchronisation
• PWM power convertors
• distributed control
• protocols
• pulse width modulation
• switching convertors
• field programmable gate arrays
• precision timing protocol
• distributed control nodes
• nonconventional digital pulse-width modulation technique
• phase accumulator carrier pulse-width modulation
• carrier synchronisation
• three-node test bench
• single clock cycle precision
• data acquisition system
• modular multilevel PHIL amplifiers
• modular control
• multilevel power hardware-in-the-loop amplifiers
• PWM carrier wave