Research and Design of Nand Flash Array From Host to Flash Translation Layer

Abstract

Given the inherent limitations of flash memory, solid-state storage devices require a host controller and a flash translation layer (FTL) to address two major conflicts: the conflict between the limited erase endurance of flash memory and the expectation of longer usage time and the conflict between the insufficient per-die bandwidth of flash memory and the exponential growth in data throughput.This paper presents a hybrid architecture implemented with FPGA logic and embedded processors. FPGA hardware acceleration is utilized to meet the requirement of high bandwidth, while the Host-FTL flash translation layer architecture is used to address the varying workload demands. By separating the storage device from the flash translation layer, the host manages the flash channel using the command and message units provided by the system.The design of Host-FTL not only implements conventional software algorithms such as address mapping, wear leveling, and bad block management but also uses a “pipeline” strategy for regular writes and a “parallel page group” strategy for large file writes, after analyzing the bandwidth bottleneck of the system. The channel-level RAID array enhances data security, and the localized wear leveling increases the total amount of written data in the solid-state disk array.

Keywords

• NAND Flash
• HOST-FTL
• FPGA
• wear leveling
• solid-state storage